1. Field of the Invention
The present invention relates to a digital processor.
2. Description of the Related Art
The manner in which the conventional digital processor refers to an external memory will be described with reference to FIG. 6.
In FIG. 6, 601 denotes a digital processor. The digital processor 601 includes as main components an instruction memory 602, a program control unit 603, an external memory reference control circuit 604 for controlling reference to the external memory, an arithmetic unit for actually executing the operation, and an operation block 605 having a register for storing data, an internal memory, and the like. The program control unit 603 contains a sequencer 603a which sequentially executes an instruction code read from the external memory 602 by outputting an address (PC) to the instruction memory 602 in synchronization with a clock 1 (CLK 1) and a decoder 603B which analyzes the instruction code and outputs various operands. The various operands used herein denote an address (adrs), data, and a control signal (ctl) such as a write signal.
Now, the manner in which the digital processor 601 operates to refer to the external memory 606 will be described.
FIG. 7 is a timing chart based on a read cycle involved in an external memory cycle done in the digital processor 601.
The digital processor 601 realizes an asynchronous memory cycle based on an acknowledge signal. In operation, when the external memory reference instruction read by the sequencer 603a is executed, the external memory reference control circuit 604 serves to output the external address (adrs) and the control signal (ctl) such as a write signal. The sequencer 603a stops execution of the next instruction and keeps a WAIT cycle until supplied with an acknowledge signal sent from the external memory 606. In the READ cycle, the data is read on a leading edge of a first clock 1 (CLK 1) after the acknowledge signal is supplied.
The above-mentioned control is realized by the program control unit 603 having the sequencer 603a, the decoder 603b, and the external memory reference control circuit 604.
The foregoing digital processor 601 is, however, required to have too long a WAIT cycle if the processor refers to a memory or a device requiring a long access time, resulting in degradation of a throughput of the total processing. Further, in case the digital processor 601 executes an instruction for continuously transferring a large amount of data between the external memory and the digital processor 601 itself, the throughput is further degraded.
While the external memory reference instruction is being executed, a resource reference instruction is often issued to the program control unit 603 for referring to a resource occupied by the instruction being executed. In general, since the resource is exclusively controlled, the program control unit 603 is disadvantageously required to execute a meaningless instruction (NOP instruction) until the external memory cycle is terminated.